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INTEGRATED CIRCUITS
DATA SHEET
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* The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications * The IC06 74HC/HCT/HCU/HCMOS Logic Package Information * The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT7030 9-bit x 64-word FIFO register; 3-state
Product specification File under Integrated Circuits, IC06 December 1990
Philips Semiconductors
Product specification
9-bit x 64-word FIFO register; 3-state
FEATURES * Synchronous or asynchronous operation * 3-state outputs * Master-reset input to clear control functions * 33 MHz (typ.) shift-in, shift-out rates with or without flags * Very low power consumption * Cascadable to 25 MHz (typ.) * Readily expandable in word and bit dimensions * Pinning arranged for easy board layout: input pins directly opposite output pins * Output capability: standard * ICC category: LSI GENERAL DESCRIPTION The 74HC/HCT7030 are high-speed Si-gate CMOS devices specified in compliance with JEDEC standard no. 7A. The 74HC/HCT7030 is an expandable, First-In First-Out (FIFO) memory organized as 64 words by 9 bits. A 33 MHz data-rate makes it ideal for high-speed applications. Even at high frequencies, the ICC dynamic is very low (fmax = 18 MHz; VCC = 5 V produces a dynamic ICC of 80 mA). If the device is not continuously operating at fmax, then ICC will decrease proportionally. With separate controls for shift-in (SI) and shift-out (SO), reading and writing operations are completely independent, allowing synchronous and asynchronous data transfers. Additional controls include a master-reset input (MR) and an output enable input (OE). Flags for data-in-ready (DIR) and data-out-ready (DOR) indicate the status of the device. Devices can be interconnected easily to expand word and bit dimensions. All output pins are directly opposite the corresponding input pins thus simplifying board layout in expanded applications. INPUTS AND OUTPUTS Data inputs (D0 to D8) As there is no weighting of the inputs, any input can be assigned as the MSB. The size of the FIFO memory can be reduced from the 9 x 64 configuration, i.e. 8 x 64, 7 x 64, down to 1 x 64, by tying unused data input pins to VCC or GND. Master-reset (MR) Data outputs (Q0 to Q8)
74HC/HCT7030
As there is no weighting of the outputs, any output can be assigned as the MSB. The size of the FIFO memory can be reduced from the 9 x 64 configuration as described for data inputs. In a reduced format, the unused data output pins must be left open circuit.
When MR is LOW, the control functions within the FIFO are cleared, and data content is declared invalid. The data-in-ready (DIR) flag is set HIGH and the data-out-ready (DOR) flag is set LOW. The output stage remains in the state of the last word that was shifted out, or in the random state existing at power-up. Status flag outputs (DIR, DOR) Indication of the status of the FIFO is given by two status flags, data-in-ready (DIR) and data-out-ready (DOR): DIR DIR = HIGH indicates the input stage is empty and ready to accept valid data = LOW indicates that the FIFO is full or that a previous shift-in operation is not complete (busy)
DOR = HIGH assures valid data is present at the outputs Q0 to Q8 (does not indicate that new data is awaiting transfer into the output stage) DOR = LOW indicates the output stage is busy or there is no valid data Shift-in control (SI) Data is loaded into the input stage on a LOW-to-HIGH transition of SI. A HIGH-to-LOW transition triggers an automatic data transfer process (ripple through). If SI is held HIGH during reset, data will be loaded at the rising edge of the MR signal. Shift-out control (SO) A LOW-to-HIGH transition of SO causes the DOR flags to go LOW. A HIGH-to-LOW transition of SO causes upstream data to move into the output stage, and empty locations to move towards the input stage (bubble-up). Output enable (OE) The outputs Q0 to Q8 are enabled when OE = LOW. When OE = HIGH the outputs are in the high impedance OFF-state.
December 1990
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Philips Semiconductors
Product specification
9-bit x 64-word FIFO register; 3-state
QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C; tr = tf = 6 ns
74HC/HCT7030
TYPICAL SYMBOL tPHL/ tPLH PARAMETER propagation delay MR to DIR and DOR SO to Qn fmax CI CP Notes 1. CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD x VCC2 x fi + (CL x VCC2 x fo) where: fi = input frequency in MHz fo = output frequency in MHz (CL x VCC2 x fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC - 1.5 V ORDERING INFORMATION See "74HC/HCT/HCU/HCMOS Logic Package Information". maximum clock frequency SI and SO input capacitance power dissipation capacitance per package notes 1 and 2 CONDITIONS HC CL = 15 pF; VCC = 5 V 21 36 33 3.5 660 26 40 29 3.5 660 ns ns MHz pF pF HCT UNIT
December 1990
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Philips Semiconductors
Product specification
9-bit x 64-word FIFO register; 3-state
PIN DESCRIPTION PIN NO. 1, 2, 14 3 4 5, 6, 7, 8, 9, 10, 11, 12, 13 15 24, 23, 22, 21, 20, 19, 18, 17, 16 25 26 27 28 Note SYMBOL GND DIR SI D0 to D8 OE Q0 to Q8 DOR SO MR VCC NAME AND FUNCTION ground (0 V) data-in-ready output
74HC/HCT7030
shift-in input (LOW-to-HIGH, edge-triggered) parallel data inputs output enable input (active LOW) 3-state parallel data outputs data-out-ready output shift-out input (HIGH-to-LOW, edge-triggered) asynchronous master-reset input (active LOW) positive supply voltage
1. Pin 14 must be connected to GND. Pins 1 and 2 can be left floating or connected to GND, however it is not allowed to let current flow in either direction between pins 1, 2 and 14.
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
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Philips Semiconductors
Product specification
9-bit x 64-word FIFO register; 3-state
74HC/HCT7030
Fig.4 Functional diagram.
APPLICATIONS * High-speed disc or tape controller * Video timebase correction * A/D output buffers * Voice synthesis * Input/output formatter for digital filters and FFTs * Bit-rate smoothing
December 1990
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Philips Semiconductors
Product specification
9-bit x 64-word FIFO register; 3-state
FUNCTIONAL DESCRIPTION Data input Following power-up, the master-reset (MR) input is pulsed LOW to clear the FIFO memory (see Fig.8). The data-in-ready flag (DIR = HIGH) indicates that the FIFO input stage is empty and ready to receive data. When DIR is valid (HIGH), data present at D0 to D8 can be shifted-in using the SI control input. With SI = HIGH, data is shifted into the input stage and a busy indication is given by DIR going LOW. The data remains at the first location in the FIFO until SI is set to LOW. With SI = LOW data moves through the FIFO to the output stage, or to the last empty location. If the FIFO is not full after the SI pulse, DIR again becomes valid (HIGH) to indicate that space is available in the FIFO. The DIR flag remains LOW if the FIFO is full (see Fig.6). The SI pulse must be made LOW in order to complete the shift-in process. With the FIFO full, SI can be held HIGH until a shift-out (SO) pulse occurs. Then, following a shift-out of data, an empty location appears at the FIFO input and DIR goes HIGH to allow the next data to be shifted-in. This remains at the first FIFO location until SI again goes LOW (see Fig.7). Data transfer After data has been transferred from the input stage of the FIFO following SI = LOW, data moves through the FIFO asynchronously and is stacked at the output end of the register. Empty locations appear at the input end of the FIFO as data moves through the device. Data output The data-out-ready flag (DOR = HIGH) indicates that there is valid data at the output (Q0 to Q8). The initial master-reset at power-on (MR = LOW) sets DOR to LOW (see Fig.8). After MR = HIGH, data shifted into the FIFO moves through to the output stage causing DOR to go HIGH. As the DOR flag goes HIGH, data can be shifted-out using the SO control input. With SO = HIGH, data in the output stage is shifted out and a busy indication is given by DOR going LOW. When SO is made LOW, data moves through the FIFO to fill the output stage and an empty location appears at the input stage. When the output stage is filled DOR goes HIGH, but if the last of the valid data has been shifted out leaving the FIFO empty the DOR flag remains LOW (see Fig.9). With the FIFO empty, the last word that was shifted-out is latched at the output Q0 to Q8. December 1990 6
74HC/HCT7030
With the FIFO empty, the SO input can be held HIGH until the SI control input is used. Following an SI pulse, data moves through the FIFO to the output stage, resulting in the DOR flag pulsing HIGH and a shift-out of data occurring. The SO control must be made LOW before additional data can be shifted out (see Fig.10). High-speed burst mode If it is assumed that the shift-in/shift-out pulses are not applied until the respective status flags are valid, it follows that the shift-in/shift-out rates are determined by the status flags. However, without the status flags a high-speed burst mode can be implemented. In this mode, the burst-in/burst-out rates are determined by the pulse widths of the shift-in/shift-out inputs and burst rates of 35 MHz can be obtained. Shift pulses can be applied without regard to the status flags but shift-in pulses that would overflow the storage capacity of the FIFO are not allowed (see Figs 11 and 12). Expanded format With the addition of a logic gate, the FIFO is easily expanded to increase word length (see Fig.17). The basic operation and timing are identical to a single FIFO, with the exception of an additional gate delay on the flag outputs. If during application, the following occurs: * SI is held HIGH when the FIFO is empty, some additional logic is required to produce a composite DIR pulse (see Figs 7 and 18). * SO is held HIGH when the FIFO is full, some additional logic is required to produce a composite DOR pulse (see Figs 10 and 18). Due to the part-to-part spread of the ripple through time, the flag signals of FIFOA and FIFOB will not always coincide and the AND-gate will not produce a composite flag signal. The solution is given in Fig.18. The "7030" is easily cascaded to increase the word capacity and no external components are needed. In the cascaded configuration, all necessary communications and timing are performed by the FIFOs. The intercommunication speed is determined by the minimum flag pulse widths and the flag delays. The data rate of cascaded devices is typically 25 MHz. Word-capacity can be expanded to and beyond 128-words x 9-bits (see Fig.19).
December 1990
Philips Semiconductors
9-bit x 64-word FIFO register; 3-state
7
(see control flip-flops) (1) LOW on S input of flip-flops FS, FB and FP will set Q output to HIGH independent of state on R input. (2) LOW on R input to FF1 to FF64 will set Q output to LOW independent of state on S input.
74HC/HCT7030
Product specification
Fig.5 Logic diagram.
Philips Semiconductors
Product specification
9-bit x 64-word FIFO register; 3-state
DC CHARACTERISTICS FOR 74HC For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: standard ICC category: LSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HC SYMBOL PARAMETER min. tPHL/ tPLH propagation delay MR to DIR, DOR propagation delay SI to DIR propagation delay SO to DOR propagation delay DOR to Qn propagation delay SO to Qn propagation delay/ ripple through delay SI to DOR propagation delay/ bubble-up delay SO to DIR 3-state output enable OE to Qn 3-state output disable OE to Qn output transition time +25 typ. 69 25 20 77 28 22 102 37 30 11 4 3 113 41 33 2.5 0.9 0.7 3.3 1.2 1.0 52 19 15 50 18 14 19 7 6 50 10 9 14 5 4 -40 to +85 -40 to +125 max. 315 63 54 355 71 60 475 95 81 55 11 9 520 104 88 12 2.4 1.9 15 3.0 2.4 265 53 45 225 45 38 110 22 19 75 15 13 ns
74HC/HCT7030
TEST CONDITIONS UNIT VCC WAVEFORMS (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Fig.8
max. min. max. min. 210 42 36 235 47 40 315 63 54 35 7 6 345 69 59 8.0 1.6 1.3 10.0 2.0 1.6 175 35 30 150 30 26 75 15 13 65 13 11 265 53 45 295 59 50 395 79 67 45 9 8 430 86 73 10 2.0 1.6 12 2.5 2.0 220 44 37 190 38 33 95 19 16
tPHL/ tPLH
ns
Fig.6
tPHL/ tPLH
ns
Fig.9
tPHL/ tPLH
ns
Fig.10
tPHL/ tPLH
ns
Fig.14
tPLH
s
Fig.10
tPLH
s
Fig.7
tPZH/ tPZL
ns
Fig.16
tPHZ/ tPLZ
ns
Fig.16
tTHL/ tTLH
ns
Fig.14
tW
SI pulse width HIGH or LOW
ns
Fig.6
December 1990
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Philips Semiconductors
Product specification
9-bit x 64-word FIFO register; 3-state
74HC/HCT7030
Tamb (C) 74HC SYMBOL PARAMETER min. tW SO pulse width HIGH or LOW DIR pulse width HIGH DOR pulse width HIGH MR pulse width LOW removal time MR to SI set-up time Dn to SI hold time Dn to SI maximum clock pulse frequency SI, SO burst mode maximum clock pulse frequency SI, SO using flags maximum clock pulse frequency SI, SO cascaded 100 20 17 10 5 4 10 5 4 70 14 12 80 16 14 -35 -7 -6 135 27 23 +25 typ. 33 12 10 47 17 14 47 17 14 22 8 6 24 8 7 -36 -13 -10 44 16 13 9.9 30 36 9.9 30 36 7.6 23 27 145 29 25 145 29 25 -40 to +85 -40 to +125 max. ns UNIT
TEST CONDITIONS VCC WAVEFORMS (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Fig.9
max. min. max. min. 125 25 21 8 4 3 8 4 3 90 18 15 100 20 17 -45 -9 -8 170 34 29 2.8 14 16 2.8 14 16 2.2 11 13 180 36 31 180 36 31 150 30 26 8 4 3 8 4 3 105 21 18 120 24 20 -55 -11 -9 205 41 35 2.4 12 14 2.4 12 14 1.8 9.2 11
tW
220 44 38 220 44 38
ns
Fig.7
tW
ns
Fig.10
tW
ns
Fig.8
trem
ns
Fig.15
tsu
ns
Fig.13
th
ns
Fig.13
fmax
MHz
Figs 11 and 12
fmax
MHz
Figs 6 and 9
fmax
MHz
Figs 6 and 9
December 1990
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Philips Semiconductors
Product specification
9-bit x 64-word FIFO register; 3-state
DC CHARACTERISTICS FOR 74HCT For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: standard ICC category: LSI
74HC/HCT7030
Note to HCT types The value of additional quiescent supply current (ICC) for a unit load of 1 is given in the family specifications. To determine ICC per input, multiply this value by the unit load coefficient shown in the table below. INPUT OE SI Dn MR SO UNIT LOAD COEFFICIENT 1.00 1.50 0.75 1.50 1.50
AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HCT SYMBOL PARAMETER +25 -40 to +85 -40 to +125 max. 63 74 101 117 18 2.4 ns ns ns ns ns s 4.5 4.5 4.5 4.5 4.5 4.5 Fig.8 Fig.6 Fig.9 Fig.14 Fig.10 Fig.10 UNIT VCC WAVEFORMS (V) TEST CONDITIONS
min. typ. max. min. max. min. tPHL/ tPLH tPHL/ tPLH tPHL/ tPLH tPHL/ tPLH tPHL/ tPLH tPLH propagation delay MR to DIR, DOR propagation delay SI to DIR propagation delay SO to DOR propagation delay SO to Qn propagation delay DOR to Qn propagation delay/ripple through delay SI to DOR propagation delay/ bubble-up delay SO to DIR 3-state output enable OE to Qn 3-state output disable OE to Qn output transition time 30 29 39 46 7 0.9 51 49 67 78 12 1.6 53 61 84 98 15 2.0
tPLH
1.2
2.0
2.5
3.0
s
4.5
Fig.7
tPZH/ tPZL tPHZ/ tPLZ tTHL/ tTLH
20 19 7
35 35 15
44 44 19
53 53 22
ns ns ns
4.5 4.5 4.5
Fig.16 Fig.16 Fig.14
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Philips Semiconductors
Product specification
9-bit x 64-word FIFO register; 3-state
74HC/HCT7030
Tamb (C) 74HCT SYMBOL PARAMETER +25 -40 to +85 -40 to +125 max. ns ns 56 53 ns ns ns ns ns ns MHz UNIT
TEST CONDITIONS VCC WAVEFORMS (V) 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 Fig.6 Fig.9 Fig.7 Fig.10 Fig.8 Fig.15 Fig.13 Fig.13 Figs 11 and 12
min. typ. max. min. max. min. tW tW tW tW tW trem tsu th fmax SI pulse width HIGH or LOW SO pulse width HIGH or LOW DIR pulse width HIGH DOR pulse width HIGH MR pulse width LOW removal time MR to SI set-up time Dn to SI hold time Dn to SI maximum clock pulse frequency SI, SO burst mode maximum clock pulse frequency SI, SO using flags maximum clock pulse frequency SI, SO cascaded 12 15 7 6 18 18 -5 30 15 6 9 22 20 10 10 -16 18 26 37 35 15 19 6 5 23 23 -4 38 12 46 44 18 22 6 5 27 27 -4 45 10
fmax
15
26
12
10
MHz
4.5
Figs 6 and 9
fmax
13
22
10
8.6
MHz
4.5
Figs 6 and 9
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Philips Semiconductors
Product specification
9-bit x 64-word FIFO register; 3-state
AC WAVEFORMS Shifting in sequence FIFO empty to FIFO full
74HC/HCT7030
Notes to Fig.6 1. DIR initially HIGH; FIFO is prepared for valid data. 2. SI set HIGH; data loaded into input stage. 3. DIR drops LOW, input stage "busy". 4. SI set LOW; data from first location "ripple through". 5. DIR goes HIGH, status flag indicates FIFO prepared for additional data. 6. Repeat process to load 2nd word through to 64th word into FIFO.
(1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V.
7. DIR remains LOW; with attempt to shift into full FIFO, no data transfer occurs.
Fig.6
Waveforms showing the SI input to DIR output propagation delay. The SI pulse width and SI maximum pulse frequency.
With FIFO full; SI held HIGH in anticipation of empty location Notes to Fig.7 1. FIFO is initially full, shift-in is held HIGH. 2. SO pulse; data in the output stage is unloaded, "bubble-up process of empty locations begins". 3. DIR HIGH; when empty location reached input stage, flag indicates FIFO is prepared for data input. 4. DIR returns to LOW; FIFO is full again. 5. SI brought LOW; necessary to complete shift-in process, DIR remains LOW, because FIFO is full.
(1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.7
Waveforms showing bubble-up delay, SO input to DIR output and DIR output pulse width.
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Philips Semiconductors
Product specification
9-bit x 64-word FIFO register; 3-state
Master reset applied with FIFO full
74HC/HCT7030
Notes to Fig.8 1. DIR LOW, output ready HIGH; assume FIFO is full. 2. MR pulse LOW; clears FIFO. 3. DIR goes HIGH; flag indicates input prepared for valid data. 4. DOR drops LOW; flag indicates FIFO empty.
(1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.8
Waveforms showing the MR input to DIR, DOR output propagation delays and the MR pulse width.
Shifting out sequence; FIFO full to FIFO empty Notes to Fig.9 1. DOR HIGH; no data transfer in progress, valid data is present at output stage. 2. SO set HIGH; results in DOR going LOW. 3. DOR drops LOW; output stage "busy". 4. SO is set LOW; data in the input stage is unloaded, and new data replaces it as empty location "bubbles-up" to input stage. 5. DOR goes HIGH; transfer process completed, valid data present at output after the specified propagation delay.
(1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V.
6. Repeat process to unload the 3rd through to the 64th word from FIFO. 7. DOR remains LOW; FIFO is empty.
Fig.9
Waveforms showing the SO input to DIR output propagation delay. The SO pulse width and SO maximum pulse frequency.
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Philips Semiconductors
Product specification
9-bit x 64-word FIFO register; 3-state
With FIFO empty; SO is held HIGH in anticipation
74HC/HCT7030
Notes to Fig.10 1. FIFO is initially empty, SO is held HIGH. 2. SI pulse; loads data into FIFO and initiates ripple through process. 3. DOR flag signals the arrival of valid data at the output stage. 4. Output transition; data arrives at output stage after the specified propagation delay between the rising edge of the DOR pulse to the Qn output. 5. DOR goes LOW; FIFO is empty again. 6. SO set LOW; necessary to complete shift-out process. DOR remains LOW, because FIFO is empty.
(1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.10 Waveforms showing ripple through delay SI input to DOR output, DOR output pulse width and propagation delay from the DOR pulse to the Qn output.
Shift-in operation; high-speed burst mode
In the high-speed mode, the burst-in rate is determined by the minimum shift-in HIGH and shift-in LOW specifications. The DIR status flag is a don't care condition, and a shift-in pulse can be applied regardless of the flag. A SI pulse which would overflow the storage capacity of the FIFO is ignored. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.11 Waveforms showing SI minimum pulse width and SI maximum pulse frequency, in high-speed shift-in burst mode.
December 1990
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Philips Semiconductors
Product specification
9-bit x 64-word FIFO register; 3-state
Shift-out operation; high-speed burst mode
74HC/HCT7030
In the high-speed mode, the burst-out rate is determined by the minimum shift-out HIGH and shift-out LOW specifications. The DOR flag is a don't care condition and a SO pulse can be applied without regard to the flag. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.12 Waveforms showing SO minimum pulse width and maximum pulse frequency, in high-speed shift-out burst mode.
The shaded areas indicate when the input is permitted to change for predictable output performance. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.13 Waveforms showing hold and set-up times for Dn input to SI input.
December 1990
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Philips Semiconductors
Product specification
9-bit x 64-word FIFO register; 3-state
74HC/HCT7030
(1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V.
(1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.14 Waveforms showing SO input to Qn output propagation delays and output transition time.
Fig.15 Waveforms showing the MR input to SI input removal time.
(1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.16 Waveforms showing the 3-state enable and disable times for input OE.
December 1990
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Philips Semiconductors
Product specification
9-bit x 64-word FIFO register; 3-state
APPLICATION INFORMATION
74HC/HCT7030
The PC74HC/HCT7030 is easily expanded to increase word length. Composite DIR and DOR flags are formed with the addition of an AND gate. The basic operation and timing are identical to a single FIFO, with the exception of an added gate delay on the flags.
Fig.17 Expanded FIFO for increased word length; 64 words x 18 bits.
This circuit is only required if the SI input is constantly held HIGH, when the FIFO is empty and the automatic shift-in cycles are started or if SO output is constantly held HIGH, when the FIFO is full and the automatic shift-out cycles are started (see Figs 7 and 10).
Fig.18 Expanded FIFO for increased word length.
December 1990
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Philips Semiconductors
Product specification
9-bit x 64-word FIFO register; 3-state
Expanded format
74HC/HCT7030
Fig.19 shows two cascaded FIFOs providing a capacity of 128 words x 9 bits. Fig.20 shows the signals on the nodes of both FIFOs after the application of a SI pulse, when both FIFOs are initially empty. After a rippled through delay, data arrives at the output of FIFOA. Due to SOA being HIGH, a DOR pulse is generated. The requirements of SIB and DnB are satisfied by the DORA pulse width and the timing between the rising edge of DORA and QnA. After a second ripple through delay, data arrives at the output of FIFOB. Fig.21 shows the signals on the nodes of both FIFOs after the application of a SOB pulse, when both FIFOs are initially full. After a bubble-up delay a DIRB pulse is generated, which acts as a SOA pulse for FIFOA. One word is transferred from the output of FIFOA to the input of FIFOB. The requirements of the SOA pulse for FIFOA is satisfied by the pulse width of DORB. After a second bubble-up delay an empty space arrives at DnA, at which time DIRA goes HIGH. Fig.22 shows the waveforms at all external nodes of both FIFOs during a complete shift-in and shift-out sequence.
The PC74HC/HCT7030 is easily cascaded to increase word capacity without any external circuitry. In cascaded format, all necessary communications are handled by the FIFOs. Figs 17 to 19 demonstrate the intercommunication timing between FIFOA and FIFOB. Fig.22 gives an overview of pulses and timing of two cascaded FIFOs, when shifted full and shifted empty again.
Fig.19 Cascading for increased word capacity; 128 words x 9 bits.
December 1990
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Philips Semiconductors
Product specification
9-bit x 64-word FIFO register; 3-state
74HC/HCT7030
Notes to Fig.20 1. FIFOA and FIFOB initially empty, SOA held HIGH in anticipation of data. 2. Load one word into FIFOA; SI pulse applied, results in DIR pulse. 3. Data out A/data in B transition; valid data arrives at FIFOA output stage after a specified delay of the DOR flag, meeting data input set-up requirements of FIFOB. 4. DORA and SIB pulse HIGH; (ripple through delay after SIA LOW) data is unloaded from FIFOA as a result of the data output ready pulse, data is shifted into FIFOB. 5. DIRB and SOA go LOW; flag indicates input stage of FIFOB is busy, shift-out of FIFOA is complete. 6. DIRB and SOA go HIGH automatically; the input stage of FIFOB is again able to receive data, SO is held HIGH in anticipation of additional data. 7. DORB goes HIGH; (ripple through delay after SIB LOW) valid data is present one propagation delay later at the FIFOB output stage.
(1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.20 FIFO to FIFO communication; input timing under empty condition.
December 1990
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Philips Semiconductors
Product specification
9-bit x 64-word FIFO register; 3-state
74HC/HCT7030
Notes to Fig.21 1. FIFOA and FIFOB initially full, SIB held HIGH in anticipation of shifting in new data as empty location bubbles-up. 2. Unload one word from FIFOB; SO pulse applied, results in DOR pulse. 3. DIRB and SOA pulse HIGH; (bubble-up delay after SOB LOW) data is loaded into FIFOB as a result of the DIR pulse, data is shifted out of FIFOA. 4. DORA and SIB go LOW; flag indicates the output stage of FIFOA is busy, shift-in to FIFOB is complete. 5. DORA and SIB go HIGH; flag indicates valid data is again available at FIFOA output stage, SIB is held HIGH, awaiting bubble-up of empty location. 6. DIRA goes HIGH; (bubble-up delay after SOA LOW) an empty location is present at input stage of FIFOA.
(1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.21 FIFO to FIFO communication; output timing under full condition.
December 1990
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Philips Semiconductors
Product specification
9-bit x 64-word FIFO register; 3-state
74HC/HCT7030
Sequence 1 (Both FIFOs empty, starting shift-in process): After a MR pulse has been applied FIFOA and FIFOB are empty. The DOR flags of FIFOA and FIFOB go LOW due to no valid data being present at the outputs. The DIR flags are set HIGH due to the FIFOs being ready to accept data. SOB is held HIGH and two SIA pulses are applied (1). These pulses allow two data words to ripple through to the output stage of FIFOA and to the input stage of FIFOB (2). When data arrives at the output of FIFOB, a DORB pulse is generated (3). When SOB goes LOW, the first bit is shifted out and a second bit ripples through to the output after which DORB goes HIGH (4). Sequence 2 (FIFOB runs full): After the MR pulse, a series of 64 SI pulses are applied. When 64 words are shifted in, DIRB remains LOW due to FIFOB being full (5). DORA goes LOW due to FIFOA being empty. Sequence 3 (FIFOA runs full): When 65 words are shifted in, DORA remains HIGH due to valid data remaining at the output of FIFOA. QnA remains HIGH, being the polarity of the 65th data word (6). After the 128th SI pulse, DIR remains LOW and both FIFOs are full (7). Additional pulses have no effect. Sequence 4 (Both FIFOs full, starting shift-out process): SIA is held HIGH and two SOB pulses are applied (8). These pulses shift out two words and thus allow two empty locations to bubble-up to the input stage of FIFOB, and proceed to FIFOA (9). When the first empty location arrives at the input of FIFOA, a DIRA pulse is generated (10) and a new word is shifted into FIFOA. SIA is made LOW and now the second empty location reaches the input stage of FIFOA, after which DIRA remains HIGH (11). Sequence 5 (FIFOA runs empty): At the start of sequence 5 FIFOA contains 63 valid words due to two words being shifted out and one word being shifted in in sequence 4. An additional series of SOB pulses are applied. After 63 SOB pulses, all words from FIFOA are shifted into FIFOB. DORA remains LOW (12). Sequence 6 (FIFOB runs empty): After the next SOB pulse, DIRB remains HIGH due to the input stage of FIFOB being empty (13). After another 63 SOB pulses, DORB remains LOW due to both FIFOs being empty (14). Additional SOB pulses have no effect. The last word remains available at the output Qn.
Fig.22 Waveforms showing the functionality and intercommunication between two FIFOs (refer to Fig.19).
December 1990
21
Philips Semiconductors
Product specification
9-bit x 64-word FIFO register; 3-state
PACKAGE OUTLINES See "74HC/HCT/HCU/HCMOS Logic Package Outlines".
74HC/HCT7030
December 1990
22

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